1. Field of the Invention
This invention relates generally to networking and more particularly to a method and apparatus for improving the simulation and testing of a semiconductor based multi-processor system.
2. Description of the Related Art
As semiconductor chips become more dense, i.e., the gate counts on a chip becomes larger, the simulation and the testing of the semiconductor chips is becoming a bottleneck in the process. Chips having large gate counts, i.e., between 5 and 10 million, gates causes a challenge for developers because of the increased time required to simulate and test the chip circuit prior to manufacturing the chip. In turn, the increased time for the simulation and testing further exasperates the time required for the development cycle of a semiconductor processor.
Another trend occurring with the semiconductor chips being produced is that the designs are becoming more modular, where common blocks are replicated a number of times in the chip design. FIG. 1 is a simplified block diagram of a modular design of a semiconductor chip. Chip 100 includes blocks A-F, where block A is represented twice. For example, block A could be a memory that is replicated. It should be appreciated that the replication can be exactly the same block or substantially the same block.
The substantially similar blocks are still completely tested as there does not exist a simulation method or apparatus that can execute at the block level. One solution to decrease the burgeoning time for simulation and testing is not to entirely test the entire chip. However, failure to catch and fix a defect will have drastic consequences. Thus, decreased testing is not an optimal solution.
Another shortcoming of the development process is that when a change to an existing defined architecture occurs as the development process moves forward, a new structural net list is created from the beginning rather than adjusting the pre-existing netlist. To create the structural net list from the beginning incurs a large amount of time, especially for a change that may be minor. An example of a minor change is an increase or decrease in a memory size, which is a common change throughout the development process. Thus, there is a large penalty in terms of development time as a consequence of the minor change.
In view of the foregoing, there is a need to fully test a newly developed chip in an efficient manner so that the development time can be minimized. Additionally, minor changes need to be accommodated without incurring a large time penalty.